JFET's are popular transistors for use in high quality differential amplifiers. These differential amplifiers are frequently used as input stages in multistage differential circuits. When designing a differential amplifier, close matching of the transistors is normally sought. The critical specifications for such close matching are the offsets and drifts of each transistor relative to the other. It is industry practice that such differential transistor pairs be manufactured on the same substrate, so that they will be closely coupled thermally, but that is not sufficient to eliminate mismatch. It is also necessary that the transistors exhibit the same change of their input offset voltages with respect to temperature (i.e., drift). However, the variation of offset voltage with temperature in a JFET is both hard to predict and hard to control, because there are multiple, somewhat independent sources of offset in a differential pair of JFET's. In fact, JFET's have two independent sources of drift over temperature, dV.sub.p /dT and dI.sub.ss /dT, where V.sub.p is the pinch-off voltage, I.sub.ss is the source current, and T is temperature. This implies that there must be two degrees of freedom of adjustment to trim both offset and drift.
To these ends, it has been standard practice in the manufacture of integrated circuits to measure the offset of each JFET at room temperature, and then to heat up the die and re measure the offsets at another temperature. This data is then used to guide a laser trimming process in which (1) resistors in the drain leads of each JFET are trimmed to affect the ratio of currents in the FET's thus yielding zero voltage difference (i.e. offset voltage=.+-.100 mV) at room temperature and (2) resistors in the source leads of each JFET are then trimmed to an acceptable target drift as close as possible to zero (e.g., about 1 .mu.V per degree Celsius). Typically, successful trimming is defined as producing JFET pairs with a drift characteristic of less than 5 .mu.V per degree Celsius, with a 99% success rate. Unfortunately, this is a lengthy and costly procedure, since all the JFET dies or wafers have to reach temperature equilibrium at the elevated temperature before the second offset measurement can be taken.
Accordingly, it is an object of the present invention to provide a method for trimming matched FET's, in particular JFET's, that are arranged in a differential configuration, at room temperature, to minimize their offset.
A further object of the invention is to provide a method for matching the offset and offset drift of a pair of FET's (particular JFET's) at a single temperature, which maintains the match condition over a significant temperature range.
Still another object is to provide a method for matching FET offset and drift in a differential amplifier, while maximizing CMRR (common mode rejection ratio).
Yet another object of the invention is to provide a FET differential input stage wherein the FET's can be trimmed at a single temperature.